Publications:
[1] V. Stojanović, A. Ho, B. Garlepp,
F. Chen, J. Wei,
[2] A. Ho, V. Stojanović, F. Chen, C. Werner, G. Tsang, E. Alon, R. Kollipara, J. Zerbe, M.A. Horowitz, Common-Mode Backchannel Signaling System for Differential High-speed Links, submitted to IEEE Symposium on VLSI Circuits, June 2004.
[3] E. Alon, V. Stojanović, M.A. Horowitz, Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise, submitted to IEEE Symposium on VLSI Circuits, June 2004.
[4] V. Stojanovic, A. Amirkhany and M. Horowitz, Optimal Linear Precoding with Theoretical and Practical Data Rates in High-Speed Serial-Link Backplane Communication, accepted for publication at IEEE International Conference on Communications, June 2004.
[5] J. Zerbe, C. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim, W. Stonecypher, A. Ho, T. Thrush, R. Kollipara , M. Horowitz, K. Donnelly, Equalization and Clock Recovery for a 2.5 - 10Gb/s 2-PAM/4-PAM Backplane Transceiver Cell," IEEE Journal of Solid-State Circuits, Dec. 2003.
[6] V. Stojanovic and M. Horowitz “Modeling
and Analysis of High-Speed Links,” IEEE Custom Integrated Circuits
Conference, September 2003. (invited)
[7] J. Zerbe, C. Werner, V. Stojanovic, F.
Chen, J. Wei, G. Tsang, D. Kim, W. Stonecypher, A. Ho, T. Thrush, R. Kollipara
, M. Horowitz, K. Donnelly "Equalization
and Clock Recovery for a 2.5 - 10Gb/s 2-PAM/4-PAM Backplane Transceiver Cell,"
IEEE International Solid-State Circuits Conference,
Feb. 2003.
[8] R.W. Brodersen,
M.A. Horowitz, D. Markovic, B. Nikolic, V. Stojanovic "Methods
for true power minimization," IEEE/ACM
International Conference on Computer Aided Design, Nov. 2002, pp 35-42
(invited)
[9] V. Stojanovic, D.
Markovic, B. Nikolic, M. A. Horowitz and R. W. Brodersen
"Energy-Delay
Tradeoffs in Combinational Logic using Gate Sizing and Supply Voltage
Optimization," European
Solid-State Circuits Conference, September 2002.
[10] V. Stojanovic, G. Ginis,
M.A. Horowitz "Transmit
Pre-emphasis for High-Speed Time-Division-Multiplexed Serial-Link Transceiver,"
IEEE International Conference on
Communications, April 2002.
[11] C.-K.K. Yang, V. Stojanovic, S. Modjtahedi, M.A. Horowitz, W.F. Ellersick
"A
Serial-Link Transceiver Based on 8GSample/s A/D and D/A Converters in 0.25µm
CMOS,” IEEE Journal of
Solid-State Circuits, vol. 36, no. 11 , pp. 1684-1692, November 2001.
[12] W. Ellersick,
V. Stojanovic, M. Horowitz, S. Modjtahedi, C.-K.K.
Yang, “A
Serial-Link Transceiver Based on 8GSample/s A/D and D/A Converters in 0.25µm
CMOS,” IEEE International
Solid-State Circuits Conference, Feb 2001.
[13] B. Nikolic, V.G. Oklobdzija, V
Stojanovic, W. Jia, J. Chiu, M. Leung, “Improved
Sense Amplifier-Based Flip‑Flop: Design and Measurements,” IEEE
Journal of Solid-State Circuits, vol. 35, no.6, pp.876-884, June 2000.
[14] V.Stojanovic
and V.G. Oklobdzija "Comparative
Analysis of MS Latches and Flip-Flops for High-Performance and Low-Power
Systems," IEEE Journal of Solid-State Circuits, vol. 34, no. 4,
pp. 536 –548, April 1999.
[15] B. Nikolic, V. Stojanovic, V.G.Oklobdzija,
[16] V.Stojanovic,
V.G. Oklobdzija, B. Raminder, "Comparative
Analysis of Latches and Flip-Flops for High-Performance Systems," IEEE
International Conference on Computer Design,
[17] V.Stojanovic,
V.G. Oklobdzija, B. Raminder, "A Unified
Approach in the Analysis of Latches and Flip-Flops for Low-Power Systems,"
IEEE International Symposium on Low Power Electronics and Design,
Books:
V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic, N. M. Nedovic, Digital System Clocking: High-Performance and Low-Power Aspects, Wiley-IEEE Press, January 2003