Vision Processing Architecture Studies

With rapid advances in computational imaging and vision, image signal processors (ISPs) face a changing programming environment. Rather than supporting just a small number of stable applications, there is now a need to achieve high performance from high-level code to enable rapid algorithm improvements. We compare ISP architectures for this new environment by using applications written in high-level domain-specific languages for imaging, like Darkroom and Halide, and providing the capability to compile them for two different classes of architecture: programmable in time, as represented by SIMD, and programmable in space, as typified by coarse grain reconfigurable array architectures (CGRA).

Our research leads us to consider several optimizations on these two base architectures, such as register file partitioning for SIMD, bus based routing and pipelined wires for CGRA, and hierarchical organization for line buffers.

After applying the appropriate optimizations, our results have showed that, on an average, CGRA can provide 1.5x the energy efficiency and 1.4x the compute density of a SIMD solution, and 1.7x the energy efficiency and 8.2x the compute density of an FPGA. However, the cost of providing general programmability is still high: compared to an ASIC, CGRA has 5.8x worse energy and 14.4x worse area efficiency.