DRAM energy is an important component to optimize in modern computing
systems. One outstanding source of DRAM energy is the energy to fetch
data stored on cells to the row buffer, which occurs during two DRAM
operations, row activate and refresh. This work
exploits previously proposed half page row access, modifying the
wordline connections within a bank to halve the number of cells
fetched to the row buffer, to save energy in both cases. To
accomplish this, we first change the data wire connections in the
sub-array to reduce the cost of row buffer overfetch in multi-core
systems which yields a 10% energy savings and a slight 2%
performance improvement on average in quad-core systems. We also
propose charge recycling refresh, which reuses charges left over from
a prior half page refresh to refresh another half page. Our charge
recycling scheme is capable of reducing both auto- and self-refresh
energy, saving more than 15% of refresh energy at
85° C
with even
shorter refresh cycle time. Finally, we propose a refresh scheduling
scheme that can dynamically adjust the number of charge recycled half
pages, which can save up to 30% of refresh energy at
85° C.