Vladimir Stojanovic

CIS Bldg. room 216, Stanford, CA, 94305
Tel: (650) 725-3731 Fax: (810) 283-0182
vlada@stanford.edu


I am a member of the VLSI Research Group, led by prof. Prof. M.A. Horowitz. I already got my M.S.E.E. degree here at Stanford, and this is my fifth year as a  Ph.D. student. I also hold a Dipl.Ing degree in EE from University of Belgrade, Yugoslavia.
 

 

    I am currently working on Modeling, Analysis and Design of High-Speed Links, as a part of the Electrical link research project.

 

       My research interests:

  1. Modeling of noise and dynamics of integrated circuits and systems
  2. CMOS based electrical and optical interfaces for high-speed links
  3. Implementation of digital communication techniques to constrained systems such as high-speed links
  4. Applications of convex optimization techniques to digital communications, systems and VLSI integrated circuit design.
  5. Synchronization - Clock synthesis/recovery circuits (PLL and DLL)
  6. High precision circuits, samplers, calibration loops
  7. Latches, Clock distribution, high performance and low-power digital circuit design

 

Publications

Talks

Some interesting links:

  1. classes that I've taken at Stanford
  2. bibliography
  3. chips

My family homepage.

Vladimir Stojanovic


Last modified: Sun Nov 16 11:23:07 PDT 2003