Contact me at:
I am Alex Solomatnikov. I graduated with Ph.D. in
Electrical Engineering,
supervised by Professor
Mark Horowitz.
Contact me at:
I was born in the city of Kazan, Russia in 1974. I got my bachelor and master degrees from Moscow Institute of Physics and Technology (MIPT or PhysTech), Moscow, Russia in 1997 and 1998 respectively. In 1997 I joined MCST (partially acquired by Intel in 2004) where I worked on low power circuit design, cache memory design, and memory compilers.
In 2008 I completed Ph.D. in Electrical Engineering at Stanford University, California.
I am interested in computer architecture and VLSI design. At Stanford I worked on Smart Memories project. The goal of the project was to design a reconfigurable chip multiprocessor architecture that has cache coherent, streaming and transactional memory modes as well as hybrid modes.
I worked on multiprocessor simulator and related infrastructure based on Tensilica system. I designed custom extensions for Tensilica processor. I worked on overall architecture, design and verification of 55 million transistor 8-core Smart Memories test chip, fabricated in ST Microelectronics 90 nm CMOS technology.
Smart Memories test chip was ranked 1st in 2009 Design Automation Conference/International Solid State Circuits Conference Student Design Contest.
While working on Smart Memories I spent a lot of time at Tensilica where I worked with Xtensa LX reconfigurable processor system.
[1] .A. Solomatnikov, A. Firoozshahian, O. Shacham, Z. Asgar, M. Wachs, W. Qadeer, S. Richardson, M. Horowitz, "Using a Configurable Processor Generator for Computer Architecture Prototyping", accepted to in International Symposium on Microarchitecture, December 2009
[2] A. Firoozshahian, A. Solomatnikov, O. Shacham, Z. Asgar, S. Richardson, C. Kozyrakis, M. Horowitz, "A Memory System Design Framework: Creating Smart Memories", International Symposium on Computer Architecture, June 2009
[3] O. Shacham, Z. Asgar, H. Chen, A. Firoozshahian, R. Hameed, C. Kozyrakis, W. Qadeer, S. Richardson, A. Solomatnikov, D. Stark, M. Wachs, M. Horowitz, "Smart Memories Polymorphic Chip Multiprocessor", 2009 Design Automation Conference/International Solid State Circuits Conference Student Design Contest, ranked 1st
[4] J. Leverich, H. Arakida, A. Solomatnikov, A. Firoozshahian, C. Kozyrakis, "Comparative Evaluation of Memory Models for Chip Multiprocessors", ACM Transactions on Architecture and Code Optimization, pp. 1-30, vol. 5, no. 3, November 2008
[5] O. Shacham, M. Wachs, A. Solomatnikov, A. Firoozshahian, S. Richardson, M. Horowitz, "Verification of Chip Multiprocessor Memory Systems Using A Relaxed Scoreboard", IEEE/ACM International Symposium on Microarchitecture, November 2008
[6] A. Solomatnikov, A. Firoozshahian, W. Qadeer, O. Shacham, K. Kelley, Z. Asgar, M. Wachs, R. Hameed, M. Horowitz, "Chip Multi-ProcessorGenerator", Wild and Crazy Ideas session at Design Automation Conference, June 2007
[7] J. Leverich, H. Arakida, A. Solomatnikov, A. Firoozshahian, M. Horowitz, C. Kozyrakis, "Comparing Memory Systems for Chip Multiprocessors", International Symposium on Computer Architecture, June 2007
[8] A. Solomatnikov, D. Somasekhar, N. Sirisantana, K. Roy "Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family", IEEE Transactions on Very Large Scale Integration (VLSI), pp 469-476, August 2002
[9] A. Solomatnikov, D. Somasekhar, K. Roy, C. K. Koh, "Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family", International Conference on Computer Design, September 2000