This paper describes an efficient way of simulating the effects of device random mismatch on circuit transient characteristics, such as variations in delay or in frequency. The proposed method models DC random offsets as equivalent AC pseudo-noises and leverages the fast, linear periodically time-varying (LPTV) noise analysis available from RF circuit simulators. Therefore, the method can be considered as an extension to DC match analysis and offers a large speed-up compared to the traditional Monte-Carlo analysis. Although the assumed linear perturbation model is valid only for small variations, it enables easy ways to estimate correlations among variations and identify the most sensitive design parameters to mismatch, all at no additional simulation cost. Three benchmarks measuring the variations in the input offset voltage of a clocked comparator, the delay of a logic path, and the frequency of an oscillator demonstrate the speed improvement of about 100-1000x compared to a 1000-point Monte-Carlo method.
Clocked comparators have found widespread use in noise sensitive applications including analog-to-digital converters, wireline receivers, and memory bit-line detectors. However, their nonlinear, time-varying dynamics resulting in discrete output levels have discouraged the use of traditional linear time-invariant (LTI) small-signal analysis and noise simulation techniques. This paper describes a linear, time-varying (LTV) model of clock comparators that can accurately predict the decision error probability without resorting to more general stochastic system models. The LTV analysis framework in conjunction with the linear, periodically time-varying (LPTV) simulation algorithms available from RF circuit simulators can provide insights into the intrinsic sampling and decision operations of clock comparators and the major contribution sources to random decision errors. Two comparators are simulated and compared with laboratory measurements. A 90-nm CMOS comparator is measured to have an equivalent input-referred random noise of 0.73 mV,rms for dc inputs, matching simulation results with a short channel excess noise factor gamma=2.
This brief describes low-cost on-chip measurement circuits for jitter transfer and supply sensitivity of phase-locked loops (PLLs) and delay-locked loops (DLLs). Unlike previous works that measured the frequency-domain responses, the proposed circuits measure the time-domain responses of the PLL/DLL to the periodic disturbances applied to either its input clock phase or its supply voltage. A synchronous sampling technique accurately measures the PLL/DLL's periodic response while suppressing the unrelated noises and interferences via averaging. The synchronous sampler outputs either DC voltage or digital values, making it suitable for low-cost characterization and production tests. The procedure for estimating the frequency-domain transfer functions from the measured time-domain responses is outlined. The jitter transfer and supply sensitivity measurements were demonstrated with a PLL fabricated in 0.13-um CMOS. Compared with the PLL that occupied 1.1x0.46 mm2 and dissipated 36 mW from a 1.2-V supply, the on-chip measurement circuits occupied only 0.014 mm2 and dissipated only 2.6 mW.
This paper describes design methodologies for the optimal inductive peaking structures used for the 40-Gb/s serializing transmitter circuits presented in [1]. The implemented transmitter had more than 400 on-chip inductors and transformers in order to achieve the bandwidth required for the 38.4-Gb/s operation demonstrated in a 0.13um CMOS process. A bridged T-coil network with inverted mutual coupling was found more effective than the conventional T-coil with sizeable driver-side capacitance. An iterative refinement procedure that directly optimizes the circuit's large-signal transient response at the presence of the inductor parasitics and device nonlinearities via HSPICE-ASITIC joint-simulation is described. The procedure resulted in more than 3x improvement in bandwidth for the CML buffer, multiplexer, and latch circuits. It is shown that the area and the achievable bandwidth of the optimal inductive peaking structures will scale favorably with the CMOS technology trends.
A fully integrated 40-Gb/s transceiver fabricated in a 0.13-um CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low fTof 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4 times 2.9 mm2 with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2^15-1 PRBS data is 1.85 ps,rms over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 ps,rms and the measured BER of the transceiver is less than 10^-14 .
This brief presents an adaptive-bandwidth (BW) phase-locked loop (PLL) that retains the optimal jitter performance over a wide frequency range via continuous background frequency calibration. The effective center frequency of the voltage-controlled oscillator (VCO) is calibrated by adjusting the feedforward division factor while a dual-PLL architecture hides the switching transients. As a result, the core ring oscillator only needs to operate over a narrow frequency range of 2:1 that is optimal for the jitter, supply sensitivity, and charge pump current mismatch over process, voltage, and temperature (PVT) conditions. The prototype PLL was fabricated in a 0.13-um CMOS process, consumed 36 mW of power, and occupied 1.1x0.46mm^2 of area. The measured root-mean-square (RMS) tracking jitter was less than 0.2% of the reference clock period for the wide range of output frequency (2 MHz ~ 1 GHz) and multiplication factor 2^(0 ~ 9), which supports that the PLL BW scales adaptively with the reference frequency. Compared to a PLL without frequency calibration, the proposed PLL demonstrated the jitter reduction up to 80%.
A charge pump that minimises the mismatch between the charging and discharging currents and keeps the currents constant across a wide output voltage range is described. The improved current matching helps reduce the static phase offset and reference spur of a charge-pump phase-locked loop (PLL) and the constant currents help control the PLL dynamics precisely. The proposed charge pump with dual compensation circuits demonstrates current mismatch of less than 3.2% and pump-current variation of 1.7% over the output voltage ranging from 0.2 to 1.0 V in the 0.13-um CMOS process with 1.2 V supply.
A low-power, single-channel clock-edge modulated serial link has been fabricated in a standard 0.18um CMOS technology. The link core size is 343umx188um for the transmitter and 173umx83um for the receiver. The link consumes 3.12mW when operating at 270Mb/s with a 1.2V supply. The proposed link transfers all necessary signals between a graphic processor and a mobile display device over a single pair channel, thereby greatly saving the power and cost of the existing full-swing parallel lines. The proposed clock edge modulation (CEM) encoding can keep the channel DC-balanced without an additional bit overhead. Since a clock edge is present for each bit, an externel reference clock is not needed and its operating frequency can be varied without the possibility of harmonic locking typically found in referenceless clock and data recovery circuits. A simple DLL-based CEM decoder is described that recovers the data with low power consumption and high jitter tolerance. An analysis of the jitter tolerance to sinusoidal jitter is included along with measured data. The measurement results show jitter tolerance of 20UIpp with 1MHz sinusoidal jitter. The use of a push-pull voltage-mode driver further reduces the power consumption.
A 20GHz phase-locked loop with 4.9ps,pp and 0.65ps,rms jitter and -113.5dBc/Hz phase noise at 10MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-gm oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in 0.13um CMOS operates from 17.6 to 19.4GHz and dissipates 480mW.
Supply-reglulated phase-locked loops rely upon the VCO voltage regulator to maintain a low sensitivity to supply noise and hence low overall jitter. By analyzing regulator supply rejection, we show that in order to simultaneously meet the bandwidth and low dropout requirements, previous regulator implementations used in supply-regulated PLLs suffer from unfavorable trade-offs between power supply rejection and power consumption. We therefore propose a compensation technique that places the regulator's amplifier in a local replica feedback loop, stabilizing the regulator by increasing the amplifier bandwidth while lowering its gain. Even though the forward gain of the amplifier is reduced, supply noise affects the replica output in addition to the actual output, and therefore the amplifier's gain to reject supply noise is effectively restored.
This paper describes the design and implementation of a fully integrated 10Gb Ethernet transceiver in a 0.13um CMOS process using a single 1.2V supply. A coarse control algorithm that combines a voltage range monitoring circuit with a frequency lock detector provides a robust operation against process, voltage, and temperature (PVT) variations for a VCO with a ring oscillator. With the use of a blind oversampling DPLL architecture, four channels of XAUI transceivers can share a single PLL, eliminating the clock synchronization problem between channels. Also, the total number of clock domains for the entire chip is reduced to three, making the integration of the XAUI with the 10G transceiver simpler. The test chip consumes 898mW from a 1.2V supply.
This article addresses issues with designing a blind oversampling clock-and-data recovery unit (CDR) that meets jitter tolerance specifications. Asymptotic limits on jitter tolerance are derived assuming ideal phase detection based on a priori statistics of the received signal, proving that the coarse timing resolution of blind oversampling CDRs is not the main performance limiter. Instead, the effectiveness of a blind oversampling CDR relies on a phase detection algorithm that makes good estimates on the signal's statistics with a finite number of discrete samples and at reasonable hardware costs. The statistical simulation methodology outlined here enables quick verification of the bit-error rate and comparisons between the jitter tolerances of various blind oversampling CDR architectures.
A PLL/DLL design with adaptively-adjusting bandwidth enables optimal performance over a wide range of frequency and against process, voltage, and temperature variations. A design methodology of such adaptive-bandwidth PLLs and DLLs is described. To assess the impact of each circuit parameter directly, we derived a discrete-time, open-loop dynamic model of the PLL/DLL that characterizes the change in output variables in response to the sampled error and we expressed the adaptive-bandwidth criteria in terms of the open-loop gains, instead of the traditional closed-loop parameters, wn and zeta. Applying these criteria, we derived the scaling equations of the charge-pump current and the filter resistance that achieve adaptive bandwidth in charge-pump PLL/DLLs.
A self-biased phase-locked loop (PLL) uses a sampled feedforward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, process, voltage, and temperature. The PLL achieves a multiplication range of 1-4096 with less than 1.7% output jitter. Fabricated in 0.13-um CMOS, the area is 0.182mm^2 and the supply is 1.5V.
This paper extends the application of adaptive power-supply regulation to serial links. The adaptive supply maximizes the energy-efficiency of the I/O circuits and serves as a global bias to scale the link properties optimally with the bitrate. Parallelism in transceivers and the use of multiphase clocks increase the bitrate to a multiple of the clock frequency and, hence, enable the low frequency low-voltage operation to reduce power while meeting the specified bitrate. Two key designs to enable this power saving are presented: parallelized transceivers for low-voltage operation and dual-loop architecture phase/delay-locked loop for multiphase clock distribution. A prototype chip fabricated in 0.25um CMOS process operates at 0.65-5.0 Gb/s while dissipating 9.7-380 mW.
This paper roposes a digital controller for adaptive power-supply regulation that uses sliding control, which is a widely used technique in switching power supplies for its fast transient response and robust stability. A novel reformulation of the sliding control law enables a simple and power-efficient digital implementation. The reference circuit can be either a delay line or a ring oscillator, and the sensor circuits for both cases are discussed. The prototype chip fabricated in 0.25-um CMOS technology demonstrates a power efficiency of 89~95% over the regulated voltage range of 1.1~2.3V.
This paper presents a low-power high-speed CMOS signaling interface that operates off of an adaptively regulated supply. A feedback loop adjusts the supply voltage on a chain of inverters until the delay through the chain is equal to half of the input period. This voltage is then distributed to the I/O subsystem through an efficient switching power-supply regulator. Dynamically scaling the supply with respect to frequency leads to a simple and robust design consisting mostly of digital CMOS gates, while enabling maximum energy efficiency. The interface utilizes high-impedance drivers for operation across a wide range of voltages and frequencies, a dual-loop delay-locked loop for accurate timing recovery, and an input receiver whose bandwidth tracks with the I/O frequency to filter out high-frequency noise. Test chips fabricated in a 0.35-um CMOS technology achieve transfer rates of 0.2-1.0 Gb/s/pin with a regulated supply ranging from 1.3-3.2V.
This paper proposes a circuit optimization approach that can ease the computational burden on the simulation-based circuit optimizers by leveraging simple design equations that reflect the designer¿s intent. The technique is inspired by continuation methods (a.k.a. homotopy) in numerical analysis where a hard problem is solved by constructing an easier problem first and gradually refining its solution to that of the hard problem. In a circuit optimization context, the designer¿s simplified equations for the circuit serve as the easier problem. These simplified design equations are easy to write as they need not be completely accurate and have intuitive, well-understood solutions. Nonetheless, in several circuit examples, it was found that the designer¿s equations serve as better guidance than the conventional, fixed-point equations. As a result, the proposed approach demonstrates the better convergence to the desired solution with less computational efforts.
Leveraging the Boolean intent of digital circuits has enabled a wide set of CAD tools that helped increase the productivity of digital designers. To increase analog designers' productivity requires a similar encapsulation of designer's intent for analog circuits. We argue that linear system models serve this role for almost all analog circuits, while the variables of these models may be in some transformed domains, rather than being the direct voltage/current waveforms of the circuits. We show how using these models enable new ways to design, optimize, and validate mixed-signal circuits. Even systems that reach steady states only in a stochastic sense can be analyzed as linear systems. Then a remaining issue is to ensure that the non-linear circuit reaches the intended "linear" operating point during start-up, which can be addressed by global convergence analysis.
This paper demonstrates that the steady-state and adjoint sensitivity analyses can be extended to stochastic mixed-signal systems based on Markov chain models. The examples of such systems include digital phase-locked loops and delta-sigma data converters, of which steady-state response is statistical in nature, consisting of an ensemble of waveforms with probability distribution. For efficient Markov-chain analysis, the paper describes three methods that can limit the number of states: a state discretization scheme based on Gaussian decomposition, a state exploration algorithm that discovers the recurrent states, and a state truncation algorithm that eliminates the states with negligible stationary probabilities. The stochastic AC analysis is performed by deriving a first-order ordinary differential equation governing the perturbations in the stationary probabilities and solving it via phasor analysis. In the digital PLL and first-order delta-sigma ADC examples, the number of states was reduced by a factor of 35 and the frequency-domain phase and noise transfer functions were simulated with a 57~22,000x speed-up compared to using transient, Monte-Carlo simulations.
This paper describes an efficient method to characterize the impulse sensitivity function (ISF) of a periodic circuit via periodic AC (PAC) analysis. The paper extends the application of ISF from oscillators to other periodic circuits including flip-flops, latches, clocked comparators, and regenerative amplifiers, in order to characterize their important characteristics such as set-up and hold times, regeneration gain, metastability probability, and sampling aperture/bandwidth. Recognizing that the generalized ISF is a subset of a time-varying impulse response, the ISF is efficiently computed based on periodic time-varying system analysis techniques. Compared to the previous ISF characterization method based on transient simulations, a speed-up of ~5x is achieved.
Clocked comparators have found widespread use in noise sensitive applications such as wireline receivers, A/D converters, and memory bit-line detectors. However, their nonlinear, time-varying behavior and discrete output levels have discouraged the use of traditional small-signal noise simulation techniques such as .NOISE in SPICE. This paper asserts that the periodic noise analysis available from RF circuit simulators can provide insight into the intrinsic sampling and decision operations of clocked comparators and help develop a linear periodically time-varying (LPTV) noise model that accurately predicts the decision error probability. Two comparators are simulated and compared to labaratory measurements. A 90nm CMOS comparator is measured to have an equivalent input-referred random noise of 0.73mV,rms for DC inputs, matching simulation results with a short channel excess noise factor gamma=2.
Practical simulation and measurement methods based on impulse sensitivity functions to characterize the sampling aperture of clocked comparators are demonstrated on a 90nm CMOS testchip. The results comparing a StrongARM latch and a CML latch suggest that the StrongARM latch has a narrower aperture of 23ps but its aperture center is more sensitive to supply (65ps/V). The CML latch has a higher sampling gain of 88.8dB but a lower bandwidth of 6.8GHz.
A fully integrated 40Gb/s transceiver is implemented in a 0.13um CMOS technology. This paper addresses the challenges in designing a 20GHz input sampler, a 20GHz quadrature LC-VCO, a 20GHz bang-bang phase detector, and a 40Gb/s equalizer. The transceiver occupies 1.7x2.9mm^2 and dissipates 3.6W from a 1.45V supply. With the equalizer on, the transmit jitter of 39Gb/s 2^15-1 PRBS data is 1.85ps,rms over a wire-bonded plastic ball grid array (PBGA) package, an 8-mm RO-4350B PCB trace, an on-board 2.4mm connector and a 1m-long 2.4mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77ps,rms and the measured BER is < 10^-14.
This paper describes a method to perform linear AC analysis on mixed-signal systems with appear strongly nonlinear in the voltage domain but are linear in other variable domains. Common circuits like phase/delay-locked loops and duty-cycle correctors fall into this category, since they are designed to be linear with respect to phases, delays, and duty-cycles of the input and output clcoks, respectively. The method uses variable domain translators to change the variables to which the AC perturbation is applied and from which the AC response is measured. By utilizing the efficient periodic AC (PAC) analysis available in commericial RF simulators, the circuit's linear transfer function in the desired variable domain can be characterized without relying on extensive transient simulations. Furthermore, the variable domain translators enable the circuits to be macromodeled as weakly-nonlinear systems in the chosen domain and then converted to voltage--domain models, instead of being modeled as strongly-nonlinear systems directly.
This paper presents a frequency divider with a wide operating frequency range and a high bandwidth CML buffer intended for an 80-Gb/s serial link system. The proposed divider uses a pulsed-latch architecture that replaces the slave latch in a flip-flop based divider with a buffer. The CML buffer employs both shunt-and-double-series inductive peaking and active feedback. Implemented in a 0.13um CMOS process with fT of only 82GHz,the divider operates over a wide range of 26.5-37.5GHz with an input sensitivity of 1Vpp,diff and produces a nominal output swing of 1Vpp,diff. The CML buffer achieves a -3dB bandwidth of 73.5GHz in simulation, which is high enough to buffer an 80-Gb/s NRZ data stream. The fabricated frequency divider and clock buffers dissipate 22.5mW and 72mW, respectively, from a 1.8V supply.
This paper describes a noise-based method of estimating the effects of device random mismatch on circuit's transient response, such as delay and frequency. The proposed method models DC mismatch as equivalent AC pseudo-noise and exploits the fast periodic noise analysis (PNOISE) available in RF circuit simulators to compute the resulting variation in the circuit response. While the method relies on Gaussian mismatch distribution and linear perturbation model, it can model and analyze correlations as well as identify the most sensitive design parameter to mismatches with no additional simulation cost. Three benchmarks measuring the variations in the input offset voltage of a comparator, the delay of a logic path, and the frequency of an oscillator demonstrate the speed improvement of 100-1000x compared to a 1000-point Monte-Carlo method.
A bandpass delta-sigma interface IC for sacrificial bulk micromachined inertial sensors is presented. To achieve high resolution without precision analog circuits, the proposed architecture replaces the analog mixer of a chopper-stabilized readout amplifier with a 1-bit, 4-th order bandpass delta-sigma modulator and a digital decimator/demodulator. Leveraging the high oversampling ratio of 8192 and the supporting circuit techniques, the interface IC provides a 128-Hz, 20-bit digital output with 113dB peak SNR and 115dB dyanmic range (DR). Fabricated in 0.18um CMOS, the IC dissipates 56.1mW.
This paper presents a 20GHz phase-locked loop with 4.9ps,pp/0.65ps,rms jitter and -101.2dBc/Hz phase noise at 1MHz offset. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-gm oscillator with a coupled-microstrip resonator. Static frequency dividers made of pulsed latches operate faster than flip-flop based dividers and achieve near 2:1 frequency range. The PLL fabricated in 0.13um CMOS operates from 17.6GHz to 19.4GHz and dissipates 480mW.
This paper describes a quad 3.125Gbps transceiver focusing on digital data recovery circuits. Effect of each design parameters on jitter tolerance (JTOL) is analyzed and for better JTOL, a new phase averaging method with internal forward path is proposed. On-chip JTOL measurement circuits are implemented to characterize the transceiver performance, and it shows that the proposed method improves the JTOL about 0.1UI. Implemented in 0.13um CMOS, the transceiver tolerates up to 0.67UI of total jitter at 3.125Gbps.
This paper explores the speed horizon of CMOS technology by building a 40Gb/s transmitter in a 0.13um process with fT of 70GHz. Since such high speed is well beyond the reach of conventional CMOS link designs, the paper presents circuit techniques that use inductive peaking, negative feedback, and pulsed latches to achieve the bandwidth and timing closure required. The 38.4Gb/s 2^31-1 PRBS transmitted eye has differential voltage swing of 540mV,pp, rise time of 14ps, and jitter of 8.11ps,pp and 1.53ps,rms.
A 10Gb Ethernet transceiver chip integrated with 10Gb/s serial and quad 3.125Gb/s XAUI interfaces is implemented in 0.13um CMOS and consumes 970mW from 1.2V. A digital coarse control algorithm for VCOs reduces the VCO gains for noise immunity. A blind oversampling technique enables synthesis of the XAUI interface.
A self-biased PLL uses a sampled feed-forward filter network and a multi-stage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, and PVT. The PLL achieves a multiplication range of 1 to 4096 with <3.8% period jitter at 1.5V supply. Fabricated in 0.13um CMOS, the area is 0.182mm^2 and the supply is 1.5V.
Adaptive power-supply regulation is extended to serial links, by using 5:1 multiplexing and low-voltage transceivers for power saving, and by scaling link properties with bit rate, especially in per-pin clock recovery PLL/DLLs. The serial link operates at 0.45~3.5 Gb/s for 0.9~2.5 V supply and dissipates 9.2~197mW.
An efficient digital sliding controller for adaptive power supply regulation is presented. A widely used technique for switching power supplies is analog sliding control, and it is known for its robust stability and fast transient response. However, adaptive power supply control tries to regulate the delay and favors a digital controller over conventional analog controllers, which regulate the voltage. A novel reformulation of the sliding control law enables a simple digital implementation that also integrates the reference circuit into the sensor. The digital sliding controller operates at the regulated variable supply, so its power dissipation also scales. The prototype chip fabricated in 0.25um CMOS technology demonstrates a power efficiency of 89~95% over the regulated voltage range of 1.1V~2.3V.
A technique for designing DLLs and PLLs using CMOS buffers with a regulated supply is presented. By scaling the charge pump current and the output resistance of the regulating amplifier, the proposed loops achieve a wide bandwidth that tracks the operating frequency, a constant damping factor, large operating range and low noise sensitivity. Prototype loops designed in 0.35um CMOS processes exhibit >10x operating range and less than 1% input tracking jitter.
Adaptive power supply regulation reduces power dissipation in DSP and microprocessor cores. A technique extends this concept to a high-performance parallel input/output (I/O) interface. An inverter, used as the basic delay element in the core of a dual-loop delay-locked loop (DLL), has delay controlled by the supply voltage. This control voltage is replicated by a high-efficiency switching supply to power the rest of the interface and to maximize energy-efficient operation.
There is a need for IC chips that can support very high input/output (I/O) bandwidths. The key to high bandwidth is high per-pin I/O data rate and low power operation to enable a large number of pins to be integrated. This dissertation explores how adaptive power-supply regulation and parallelism can help minimize the link power dissipation while achieving high performance.
To maximize the energy-efficiency, the supply voltage is adaptively regulated to the minimum required for the desired frequency. The adaptive supply uses a buck regulator for efficient voltage step-down, and this regulator uses a novel digital sliding controller that monitors the link performance and adapts the voltage to process and temperature variations. Since the dynamics of the sliding controller do not depend on its operating frequency, the controller can be operated off of the adaptive supply, achieving the overall efficiency of 89-95% over the entire operating range (over 40× change in power).
The analog sections of the I/O circuits are modified to extend their operation to very low voltages. The input signals to the transmitter output stage are level-shifted to make the effective threshold voltage of the output devices zero and to mitigate the output current vanishing as the supply voltage approaches Vth. The receiver stage uses an integrating stage with no sampling switches and a charge-injection-based comparator that can operate at very low supply. Overall, the link is operational down to 0.9V with Vth of 0.55V. The timing for the links is controlled by either PLL or DLL circuitry that locally generates the needed multiphase clocks for the parallelized transceiver architecture. The area of these circuits are reduced by using the adaptive supply as the global loop to coarse-tune the frequency and using the local loops to fine-tune over a narrow range. In this architecture, the PLL design requires 52% less power and 41% less area than the DLL design with about the same jitter. The clock recovery PLLs use bangbang control and its nonlinear effects are carefully analyzed.
Prototype chips were fabricated in a 0.25µm CMOS technology. The adaptive-supply link operates from 0.65 to 5.0Gb/s. At 3.1Gb/s, the complete link dissipates only 113mW.
Last modified on Mon Dec 21 11:37:16 PST 2009.