In taking advantage of the CMOS process scaling, the number of transistors on a chip has been increasing and the complexity of a chip design continues to grow. To cope with this increased design complexity and the pressure to shorten time to market, designers must turn the proven designs in one chip into building blocks for a new design in another. While the practice of design reuse is well established for digital circuits, there still remain challenges for analog circuits. Design constraints of analog circuits are sometimes implicit, which makes porting the design to a new environment difficult and prone to failure. This research focuses on the problem of capturing analog and mixed-signal circuits and reusing them as portable modules.
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Our proposed framework, STAR (Schematic Tool for Analog Reuse), allows the designers to archive not only the sized schematics but also some of the objectives that the circuit is trying to achieve. STAR augments the schematic capture system to enable the circuit designers to annotate their schematics with special comments, called Active Comments. The designers embed predefined functions in the Active Comments to specify the goals and constraints of the circuits. An execution engine turns these comments into simulation runs to measure the circuit parameters and monitors to check the circuit's operating conditions. This facilitates design reuse because the same set of checks is automatically performed anywhere the circuit is instantiated. |
To explore what features are necessary in capturing a design and
making it portable, we constructed a prototype tool to process the
Active Comments and to automate the generation and the verification
processes. Our focus is to design portable circuits by allowing the
designers to specify the design knowledge as part of the circuit
representation. We loosen the requirement of building a fully
integrated system. Instead, we opt for implementing an engine that
can work with a different schematic system, simulators and analysis
tools. The functions used in the Active Comments may change depending
on the class of circuits being designed. Therefore, the prototype
must be flexible and extensible.
The prototype tool is composed of four layers, as shown on the right. The top-most layer, the schematic layer, implements the schematic user interface written in Tcl/Tk while the middle two layers form the library and the execution engine written in Perl. The primitive layer contains C code optimized for the calculation intensive data processing routines. By coding the functions in a general scripting language, the designers should be able to extend the library easily to enable STAR to capture a wide range of circuits.
Below are two screen shots of the schematic interface. On the left is a schematic of a charge pump circuit with an Active Comments (shown in red) to constraint the input pulsewidth. On the right is the Comments Editor that specifies the Active Comment along with a detail annotation of the constraint.
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We used the prototype framework to design and constrain a PLL targeting a 0.35um process. We later applied the system to help reuse the PLL as a component in an optical receiver testchip designed in a 0.25um process. We leveraged the Active Comments embedded in the original PLL to help guide the re-optimization process. The loop dynamics of the resulting PLL track the operating frequency, with the damping factor varying less than 12% across the frequency range of 500MHz to 1.2GHz. The framework also identified all the potential issues and verified the functionalities of the modified PLL without requiring any expertise of the designer. The ported design successfully operated at 1.2GHz.