Research
While at Stanford, I've worked on a number of projects in computer
architecture and VLSI design as part of
Mark Horowitz's
VLSI Design group. My thesis work is on
the design and analysis of reconfigurable memories as part of the
Smart Memories project.
In the future, I'm interested in continuing to work in both computer
architecture and VLSI design, as well as branching out into graphics,
networking, and CAD tool design. See my
research statement for more details.
- K. Mai, R. Ho, E. Alon, D. Liu, Y. Kim, D. Patil, M. Horowitz.
Architecture and Circuit Techniques for a 1.1GHz 16-kb Reconfigurable
Memory in 0.18um-CMOS. IEEE Journal of Solid- State
Circuits, January 2005.
- H. Lee, C. Yue, S. Palermo, K. Mai, M. Horowitz. Burst Mode
Packet Receiver using a Second Order DLL. Digest of
Technical Papers, Symposium on VLSI Circuits, June 2004.
- K. Mai, R. Ho, E. Alon, D. Liu, Y. Kim, D. Patil, M. Horowitz. Architecture and Circuit Techniques for a Reconfigurable Memory Block. Digest of Technical Papers, IEEE International Solid-State Circuits Conference, February 2004.
- R. Ho, K. Mai, M. Horowitz. Efficient On-Chip Global Interconnects. IEEE Symposium on VLSI Circuits, June 2003.
- R. Ho, K. Mai, M. Horowitz. Managing Wire Scaling: A Circuit Perspective. IEEE Interconnect Technology Conference, June 2003.
- R. Ho, K. Mai, and M. Horowitz. The Future of Wires. Proceedings of the IEEE, April 2001, pages 490-504.
- K. Mai, T. Paaske, N. Jayasena, R. Ho, W. Dally, M. Horowitz. Smart Memories: A Modular Reconfigurable Architecture. International Symposium on Computer Architecture, June 2000.
- R. Ho, K. Mai, M. Horowitz. Scaling implications for CAD. IEEE Int'l Conference for Computer-Aided Design, November 1999.
- M. Horowitz, R. Ho, K. Mai. The Future of Wires. SRC workshop (invited paper), May 1999.
- K. Mai, T. Mori, B. Amrutur, R. Ho, B. Wilburn, M. Horowitz. Low-Power SRAM Design Using Half-Swing Pulse-Mode Techniques. IEEE Journal of Solid-State Circuits, November 1998, pages 1659-1671.
- R. Ho, B. Amrutur, K. Mai, B. Wilburn, T. Mori, M. Horowitz. Applications of on-chip samplers for test and measurement of integrated circuits. IEEE Symposium on VLSI Circuits, June 1998, pages 138-139.
- T. Mori, B. Amrutur, K. Mai, M. Horowitz, I. Fukushi, T. Izawa, S. Mitarai. A 1V 0.9mW at 100MHz 2k*16b SRAM utilizing a half-swing pulsed decoder and write-bus architecture in 0.25um dual-Vt CMOS. IEEE International Solid State Circuits Conference, February 1998, pages 354-355.
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