[1] A. Solomatnikov, A. Firoozshahian, O. Shacham, Z. Asgar, M. Wachs, W. Qadeer, S. Richardson, M. Horowitz, “Using a Configurable Processor Generator for Computer Architecture Prototyping,” 42th International Symposium on Microarchitecture (MICRO 42), New York, NY, December 2009 (To Appear).
[2] A. Firoozshahian, A. Solomatnikov, O. Shacham, Z. Asgar, S. Richardson, C. Kozyrakis, M. Horowitz, “A Memory System Design Framework: Creating Smart Memories,” 36th International Symposium on Computer Architecture (ISCA 36), Austin, TX, June 2009. (PDF)
[3] O. Shacham, Z. Asgar, H. Chen, A. Firoozshahian, R. Hameed, C. Kozyrakis, W. Qadeer, S. Richardson, A. Solomatnikov, D. Stark, M. Wachs, M. Horowitz, “Smart Memories Polymorphic Chip Multiprocessor,” Proceedings of the 46th Design Automation Conference (DAC 46), San Francisco, CA, 2009 (Winner of the first prize, DAC/ISSCC Student Design Contest). (PDF)
[4] J. Leverich, H. Arakida, A. Solomatnikov, A. Firoozshahian, M. Horowitz, C. Kozyrakis, “Comparative Evaluation of Memory Models for Chip Multi-Processors,” ACM Transactions on Architecture and Code Optimization (TACO), Volume 5, Issue 3, Article No. 12, November 2008. (PDF)
[5] O. Shacahm, M. Wachs, A. Solomatnikov, A. Firoozshahian, S., Richardson, M. Horowitz, “Verification of Chip Multiprocessors Memory Systems Using a Relaxed Scoreboard,” 41st International Symposium on Microarchitecture (MICRO 41), Lake Como, Italy, November 2008. (PDF)
[6] J. Leverich, H. Arakida, A. Solomatnikov, A. Firoozshahian, M. Horowitz, C. Kozyrakis, “Comparing Memory Systems for Chip Multi-Processors,” 34th International Symposium on Computer Architecture (ISCA 34), San Diego, CA, June 2007. (PDF)
[7] A. Firoozshahian, V. Manshadi, A. Goel, B. Prabhakar, “Efficient, Fully Local Algorithm for CIOQ Switches,” 26th Annual IEEE Conference on Computer Communications (INFOCOM), Anchorage, AK, May 2007. (PDF)
[8] A. Solomatnikov, A. Firoozshahian, W. Qadeer, O, Shacham, K, Kelley, Z. Asgar, M. Wachs, R. Hameed, M. Horowitz, “Chip Multi-Processor Generator”, 44th Design Automation Conference (DAC 44), San Diego, CA, June 2007. (PDF)
[9] A. Solomatnikov, A. Firoozshahian, F. Labonte, M. Horowitz, C. Kozyrakis, K. Olukotun, K. Mai, “Smart Memories: A Configurable Processor Architecture for High Productivity Parallel Programming,” GOMACTech 05, Las Vegas, NV, April 2005. (PDF)
[10] A. Firoozshahian, Z. Navabi, M. Kamarei, “Behavioral Simulation of Bluetooth Transceiver and Radio Channel Using VHDL,” Fourth Iranian Student Conference on Electrical Engineering (ISCEE), Faculty of Engineering, University of Tehran, September 2001. (PDF)
[11] Gh. Miremadi, B. Salamat, A. Firoozshahian, “Design and Implementation of a System for Microprocessor Laboratory," Proceedings of Sharif University of Technology, 1998-1999, pp 157-166.
A. Firoozshahian, “Smart Memories: A Reconfigurable Memory System Architecture,” Ph.D. Dissertation, Electrical Engineering Department, Stanford University, 2009. (PDF)