In February of 2003, we taped out a reconfigurable memory test chip on the TSMC 0.18um process. The test chip consisted of 4 memory blocks, a low swing crossbar, and testing infrastructure circuits. The chips were successfully tested in the lab, operating at 1.1GHz clock frequency at nominal voltage of 1.8 volts (Figure 1). Results were published in 2004  ISSCC conference (K. Mai, R. Ho, E. Alon, D. Liu, Y. Kim, D. Patil, and M. Horowitz. Architecture and Circuit Techniques for a Reconfigurable Memory Block. ISSCC, February 2004).

Figure 1 - Smart Memories test chip, memory blocks and low swing crossbar

In April of 2002, we taped out a low swing interconnect test chip on the TSMC 0.18um process (Figure 2). The test chip consisted of multiple low-swing bus topologies as well as some full-swing buses for comparison. The test chip also contained a sense amplifier offset measurement block (later re-spawn on a National 0.25um process). The chips have been tested and a paper is presented at the 2003 VLSI Circuits Symposium (R. Ho, K. Mai, M. Horowitz. Efficient On-Chip Global Interconnects. IEEE Symposium on VLSI Circuits, June 2003).

Figure 2 - Low swing interconnect test chip