The Stanford Smart Memories Project is a research effort to design a single-chip computing element which provides configurable hardware support for diverse computing models and maps efficiently to future wire-limited VLSI technologies. The project involves researchers in VLSI circuits, computer architecture, compilers, operating systems, computer graphics, and computer networking.
The Smart Memory chip architecture exploits the fact that wire-delay limitations in future VLSI chips will impose a fine-grained partitioning of processors, memories, and interconnects. Adding programmable wires and logic to this inherently modular organization allows on-chip memories and communication paths to be customized to the particular computing problem at hand. This allows competitive performance with application-specific architectures but with lower cost and increased flexibility. This fine-grained partitioning of processing and memory resources also enables substantial hardware parallelism. Effectively exploiting this parallelism in the face of global wiring delays requires aggressive methods for reducing on-chip communication overhead between the various processing and memory structures.
To develop a configurable micro-architecture, we are studying diverse classes of computing problems, (such as ray tracing, multimedia and DSP, speech and voice recognition, probabilistic reasoning) and the specialized architectures that have been optimized for these problems. This will provide insight into the hardware primitives and configurable mechanisms required to implement a universal computing substrate. We are mainly interested in the requirements that such classes of applications place on the memory system of a multi-processor environment, and are investigating strategies for building a reconfigurable memory system.