In support of our MICRO-41 paper, "Verification of Chip Multi Processor Memory Systems Using A Relaxed Scoreboard", we include raw material here that can help the reader fully to evaluate and even reproduce the testbench upon which we based our results. In particular, this webpage provides links to source code for the relaxed scoreboard implementation.

List Of Attached Files

2. Connecting with the verification environment.
As briefly mentioned in the text, the relaxed scoreboard is a stand-alone Vera class, and is connected to the previously existing monitors that track transactions on the system's interfaces by leveraging the Aspect Oriented Programming (AOP) capabilities of OpenVera. The file Scoreboard_aop_links.vr contains this functionality.

3. Main implementation class.
The file Scoreboard.vr implements the relaxed scoreboard class. The main interface function for this class is AddTransToSB, which receives a processor transaction, does a virtual to physical address translation and then calls a series of checks and updates. The different checks and updates are listed in the file, each as a separate task/function.

4. Auxiliary files.
For the reader's convenience, we add Scoreboard_Address.vr, Trace_trans.vr and Trace_trans_Q.vr which, although not essential for the understanding of the code, can shed some light on the different members and methods used in the code.

Example

Relevant Links

With Great Respect,
The Authors.