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As feature sizes scale with silicon process technology and chips become increasingly complex, the design and analysis of on-chip power distribution systems becomes extremely challenging. The goals of this project are to measure supply noise as it is seen by the circuits in various locations on the chip, create systematic techniques to estimate supply noise early in the design process, design active regulation circuits to improve the quality of the on-chip supply voltage, and investigate future alternatives arising from advances in devices, circuits, and packaging.

This project is a part of the VLSI Research Group under Professor Mark Horowitz.


Current Members and Research Areas


Former Members


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Selected Talks and Posters


[Stanford] [EE Dept.]
Last modified 8/19/2006 by James Weaver, jaweaver@stanford.edu.