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This site provides information about the Circuit Optimization Project, which involves the design of a CAD framework for robust design of VLSI digital circuits and systems for optimal performance and power, here at Stanford.

This project is a joint collaboration of the Circuits Research Group, headed by Professor Mark Horowitz and the Optimization Group, led by Professor Stephen Boyd

Optimization related work at Stanford

 

As the technology continues to scale beyond 100nm, power dissipation has become a major limiting factor in circuit design. Exponential increase in leakage has limited our ability to scale supply and threshold voltages. Along with sizing, there are attempts to control the Power Supply and Vth of the devices in order to accumulate power savings without affecting the critical delay path. That makes transistor widths, supply and device threshold voltages the design variables to be chosen optimally for the given objective and constriants on Delay, Area and Power or the combination there of. We have developed a framework that allows us to derive energy-delay tradeoff curves of various circuit blocks. 

 

Another important goal of the project is to take into account the increasing statistical variations that are inherent during fabrication as we reduce the feature size. We focus on practical schemes to extend the deterministic design framework to the statistical one (using analytical models to capture the gate delay and energy statistics), resulting in robust digital circuits that have a better tolerance to statistical variations.

 

Simulations and analysis have shown that delay and power are convex functions of these design variables (or can be made convex by simple change of co-ordinates and curve fitting). This makes the problem amenable to convex optimization, for which very good theory and algorithms have been developed in the past 20 years. In particular Geometric Programming (GP) is attractive in handling circuit problems. Our aim is to design a framework that will solve this optimization problem efficiently and accurately, considerably speeding up the design time. We believe that relaxation of the original problem (which could be potentially mixed integer  - like choosing between two Vth's etc) to a continuous convex one and then iteratively snapping the results back to the integral values is a better, more efficient and faster approach than blind application of greedy graph heuristics and modifications thereof. The tradeoffs obtained at the block level can then be used as models of those blocks at the system level to achive optimal energy delay tradeoff at the micro-architecture level in a hierarchical fashion.

 

People Involved
Circuits and Architecture Research Group

• Mark Horowitz
• Dinesh Patil

Optimization Group

• Stephen Boyd
• Seung Jean Kim
• Kwangmoo Koh

Former associates

• Alvin Cheung
• Sunghee Yun

Publications and talks

Related work elsewhere

Links to other optimization projects and resources