The focus of this project is design of high performance transceivers for parallel optical links, using standard CMOS process with optical devices flip-chip bonded to the CMOS chip. Instead of using standard Transimpedance amplifiers (TIAs), we propose a new front-end receiver that uses the parasitic capacitor of the photo diode as an integrating element and resolves the incoming data with a double sampling technique.  A test chip based on this idea was fabricated in a 0.25 micron CMOS technology, and GaAs Multiple Quantum Well pin diodes that can be used both as photo detectors and modulators (MQWM), were flip_chip bonded to this chip. With a 1.6 Gb/s data rate this receiver burns only 3mWs of power.

In the next generation of this design, a complete 3x3 arrays of receivers and transmitters was implemented and used 5x multiplexing rate to enable 5Gb/s operation. Each receiver synchronizes itself with the incoming data using a new clock recovery technique that uses only data samples for phase detection, compared to conventional techniques which need extra sampling for timing recovery.

At the transmitter side multiple quantum well modulator (array of 2x3) and VCSELs (1x3) are used. to generate 9 parallel beams with 5Gb/s data rate per beam.

VLSI 2002    Chip Micrograph     Paper:  A 1.6Gbps, 3mW CMOS Receiver for Optical Communication

Optical transmitter circuits, including vertical cavity surface-emitting laser (VCSEL) and multiple-quantum-well modulator (MQWM) drivers, have been designed and fabricated in a standard 0.25mm CMOS process.  A multiplexing architecture that uses 5 differential PLL-generated clock phases produces a data stream that is 5 times the on-chip clock.  In the VCSEL driver output stage, the multiplexing is done directly at the low-impedance laser with a differential current-steering driver.  8-bit DACs are used to generate bias and modulation currents from 0-5mA with 20mA resolution.  In the MQWM driver output stage, a pseudo-nmos mux followed by low-fanout CMOS buffers are used to deliver a full 2.5V swing to the optical modulators.  At a 5Gbps data rate the VCSEL driver transmitter consumes 32mW, while the MQWM driver transmitter consumes 47mW.

Future work includes the implementation of a high voltage CMOS modulator driver.  This driver is capable of delivering a voltage swing of up to twice the nominal power supply of the chip (2Vdd) with little speed penalty.

VCSEL	MQWM

A number of research groups at Stanford are working together to create an optical router.  In true optical routing, packet level switching is performed in the optics.  In such an environment, consecutive packets can arrive at a receiver from different transmitters and the time between packets from the same transmitter to a given receiver can be extremely long.  Since different transmitters have different phase/frequency offsets with respect to a given receiver, a receiver must reacquire phase lock every packet.  When packets are only a few kilobits long, traditional clock and data recovery circuits will incur an unacceptable overhead (easily 30% or more).  While there are a few published receivers appropriate for such an application, they each have their own drawbacks.  The purpose of this project is to develop new methods of solving the 'fast phase acquisition' problem.