Electrical Links
During the 90’s, the continued scaling of chip
performance fostered a large research and development effort in high-speed chip
I/O design. We first focused on design of circuits and building blocks for
high-speed I/O. This research resulted in development of the high-speed
transmitters and receivers and associated timing loops (phase-locked loops and
clock and data recovery loops). With increasing number of links being
integrated on a chip, power efficiency of high-speed I/O emerged as an
important research area. We managed to design links that adaptively scale the
supply voltage to achieve the highly power-efficient transmission under desired
data rate.
Today internal circuits can run at 10’s of Gb/s,
but the performance of the link is limited by the bandwidth of the channel
– the electrical path from one die to the other. The obvious question now
is how to continue to scale I/O performance, and what, if anything, will
ultimately limit pin bandwidth.
Active Research:
Channel limited high-speed I/O design
Currently we are focused on the design of links that are limited by the bandwidth of the wires connecting the chips. Initially we focused on the design of multi-level transceivers (PAM4), to increase the spectral efficiency and more effectively use the available bandwidth of the channel. This effort also required the application of the equalization techniques using transmitter pre-emphasis [1], and fractional receiver equalization [2]. A related project focused on building a link composed of high-speed D/A converter based transmitter and A/D converter based receiver, to enable experimenting with more complex communication techniques and algorithms [3]. Design of 8 bit D/As and 4bit A/Ds at very high data rates (8GS/s) involved techniques for fast sampling and amplification of received data, voltage offset cancellation and precision phase interpolation.
As data rates are increasing, and more complex communication schemes are needed, our focus shifted to the noise and system modeling of high-speed I/O systems, in order to estimate the limits of electrical I/O and effectiveness of different communication techniques [4]. Our current research effort is looking at cost effective ways to increase the bit/Hz possible for channels with GHz bandwidths.
Prior Research:
High-speed
chip I/O design
The research in this area started with design of high-speed current integrating receivers [5, 6, 7] which, at sub-Gb/s data rates provided a very good approximation to the matched filter and significantly improved the robustness of the link by averaging the noise, especially timing jitter.
With data rates entering the Gb/s region, high-speed I/O design became limited by the speed of the underlying technology. This resulted in the work on multiplexed transmitters and receivers [8, 9] which managed to overcome the intrinsic gate-speed limitations. The key to these techniques lies in precise phase generation, using ring-based voltage controlled oscillators to derive multiple phases, and phase interpolators to obtain higher resolution and phase tuning. This precise phase generation also enabled the use of oversampling receivers, where each bit was 3x oversampled to provide for both data and clock recovery [10, 11].
Further improvements in high-speed I/O led to the improvements in design of timing loops, such as design of semi-digital dual delay-locked loop [12], and adaptive bandwidth PLL and DLL with regulated supply CMOS buffers, [13]. Improvements in link system design also resulted in asymmetric links for highly integrated applications, such as Tiny Terra router [14, 15, 16]. One of the first studies on the analysis of noise sources in a link and per/pin skew compensation was done for simultaneous bi-directional parallel interface [17].
The work on on-chip timing analyzer system improved the techniques for precise phase generation and interpolation and also focused on techniques for effecitive cancellation of the large offsets introduced by the regenerative latch-based receivers [18].
Power
efficient I/O design
In order to address the issue of link power efficiency, we designed several highly-efficient supply regulators [19, 20] and used them to design high-speed parallel and serial links with adaptive supply regulation, enabling highly power-efficient signaling at variable data rates [21, 22].