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Faculty AdvisorMark Horowitz
| Gates 306 | 650-725-3707 |
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | http://www-vlsi.stanford.edu/~horowitz/ |
| Research Interests: VLSI, Architecture, Biology, Microfluidics | |
Mark Horowitz received his BS and MS in Electrical Engineering from MIT in 1978, and his PhD from Stanford in 1984. Since 1984 he has been a professor at Stanford working in the area of digital integrated circuit design. While at Stanford he has led a number of processor designs including MIPS-X, one of the first processors to include an on-chip instruction cache, Torch, a statically-scheduled, superscalar processor and Flash, a flexible DSM machine. He has also worked in a number of other chip design areas including high-speed memory design, high-bandwidth interfaces, and fast floating point. In 1990 he took leave from Stanford to help start Rambus Inc, a company designing high-bandwidth memory interface technology.
Consulting ProfessorsJaeha Kim
| CIS 128 | 650-725-6599 |
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | http://www-vlsi.stanford.edu/~jaeha |
| Research Interests: Circuit Design, High-Speed Links,Analog/Mixed-Signal Methodologies | |
Jaeha Kim (S'94-M'03) received the B.S. degree in electrical engineering
from Seoul National University, Seoul, Korea, in 1997, and received the
M.S. and Ph.D. degrees in electrical engineering from Stanford
University, Stanford, CA, in 1999 and 2003, respectively. Prior to
joining Stanford, he was with True Circuits, Inc. (2001~2003), Seoul
National University in Korea (2003~2006), and Rambus, Inc (2006~2009).
His research interests include high-speed/low-power circuit design and
verification methodologies for analog and mixed-signal circuits.
Steve Richardson
| Gates 460 | 650-725-XXXX |
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | http://stanford.edu/~steveri/ |
| Research Interests: Computer Architecture, Compilers, VLSI | |
Stephen Richardson got his PhD from Stanford a long time ago, and now he's back. In the meantime, Dr. Richardson has worked at Sun Microsystems and HP research labs, where he eventually headed up a large team of hardware-oriented computer architects. Dr. Richardson was a cofounder of the original incarnation of MicroMagic (www.micromagic.com), a processor tool and design consulting firm. Dr. Richardson has published several papers and patents, including a patent covering the concept of multiplication by zero and one (US patent 5262973). If you multiply a number by zero and get zero as a result, you owe me a nickel.
StaffJim Weaver

Current StudentsFernando Amat
| Gates 330 | 650-723-9035 |
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | http://stanford.edu/~famat/ |
| Research Interests: Statistical image processing, electron tomography, biology, computer vision, optimization. | |
Fernando Amat was was born in Barcelona, Spain. He graduated from Technical University of Catalonia (UPC) with a degree in Mathematics and another degree in Telecomunnication Engineering in 2004. He came to Stanford in September, 2004 to start his PhD in Electrical Engineering. He works with professor Mark Horowitz in the are are of bioimaging and statistical learning applied to cryo-electron tomography. Professor Daphne Koller is his second advisor.
Zain Asgar
| Gates 322 | 650-644-9532 |
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | http://www.zasgar.net |
| Research Interests: Computer Architecture, VLSI, Graphics | |
Zain Asgar received his undergraduate degrees in Electrical and Computer Engineering at the University of Minnesota with Summa Cum Laude and High Distinction. He is currently pursuing his PhD under Prof. Mark Horowitz at Stanford University in the area of multiprocessors. He has worked at PMC-Sierra working on ASIC design. He is currently working at NVIDIA Corporation on the design of next generation graphics processors.
Omid Azizi
| Gates 452 | 650-XXX-XXXX |
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | http://www.stanford.edu/~oazizi |
| Research Interests: Computer Architecture, VLSI, CAD, Design for Energy-Efficiency | |
Omid Azizi has been an MS/PhD student at Stanford since September 2004, and has been working Professor Mark Horowitz since 2005. His current research focus is on the design and optimization of processor architectures for energy-efficiency, and he is also a member the Chip Generator project. Through internships, Omid has spent time at Intel's Microarchitecture Research Lab, and also at Altera, as part of the physical synthesis group. Prior to coming to Stanford, Omid studied at the Unversity of Toronto, receiving his B.A.Sc. in Computer Engineering in 2004.
Limor Bursztyn
| Gates 448 | |
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | http://pyramidal.stanford.edu/projects.html |
| Research Interests: Signal processing, neuroscience. | |
Limor Bursztyn is interested in both Electrical Engineering (with an
emphasis on signal processing) and Neuroscience. She is currently involved
in the Massively Parallel Brain Imaging project, led by Prof. Mark
Schnitzer. In this project, a system that will enable performing two-photon
imaging in 100 fruit flies (Drosophila) simultaneously is being designed.
With the help of consulting Prof. Don Stark, Limor is working on the data
acquisition, control and interface parts of the system. Limor has also been
working with Prof. Thomas Clandinin (Neurobiology), on developing
statistical signal processing techniques for using the acquired data to
infer how the fly brain analyzes visual stimuli and uses the information to
modulate behavior. Limor's PhD studies are funded by a Fulbright Science and
Technology fellowship. Prior to starting her PhD in EE at Stanford, she
received a BSc and MSc in Biomedical Engineering from Tel-Aviv University.
Han Chen
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | |
| Research Interests: Chip generator, Low-power and energy-efficient micro-architecture, recovery circuits. | |
I was born in Taiwan, but grew up in Honolulu, Hawaii. I went to University of Michigan at Ann-Arbor for bachelors and masters in electrical engineering from 1996~2000. I worked at Hal Computer Systems (Fujitsu) after graduation, and then at Synopsys till now, implementing mixed-signal intellectual properties, low-power processors and system-on-chips. I've been a corporate student at Stanford since 2005, working to get a Ph. D. while being fully employeed.
Apart from work and school, I have diversified interests. I love sports/activities that involve speed, which explains why I went sky diving and have a motorcycle license. I worship food; I dreamed of Yelping across San Francisco one day. I play tennis as regularly as time allows. I enjoy listening to music and playing musical instruments in my meager spare time. I've been building my own music recording studio as a side project for the past few years.
Sameh Galal
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | |
| Research Interests: VLSI, low power design, floating point units and computer architecture. | |
Sameh Galal: received BS in electronics engineering and computer science from the American university in Cairo, MS in electrical engineering from Stanford University where he is currently pursuing PhD. His research interests include: VLSI, low power design, floating point units and computer architecture.
Metha Jeeradit
| Gates 318 | |
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | |
| Research Interests: Circuit design, VLSI | |
Metha received his BS and MEng in Electrical and Computer Engineering from Cornell University in 2001 and 2002 respectively. He started his PhD program at Stanford in Fall 2002 before working at Rambus between 2004-2008 designing circuits for high speed links and working on circuit design methodologies. He is now working with Prof. Horowitz under the RAD initiative focusing on circuit optimization area.
Frances Lau
| Alway Building, Room M001 | (650)498-4325 |
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | http://mips.stanford.edu/public/faculty-info?personnel_id=2457 |
| Research Interests: circuit design, VLSI, computer hardware, biomedical applications | |
Frances is interested in applying techniques from circuit design, VLSI, and computer hardware to biomedical applications. She is currently focusing on molecular imaging, working on the design and development of a breast cancer imaging PET (positron emission tomography) system. This project is done in collaboration with the Molecular Imaging Instrumentation Lab at Stanford. She completed her B.A.Sc in EE at the University of Toronto in 2005 and her MSEE at Stanford in 2007, and is now an EE PhD candidate at Stanford.
Sabrina Liao
| Gates 448 | 650-725-8811 |
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | http://www.stanford.edu/~liaos |
| Research Interests: analog/mixed-signal circuit design, optoelectronics, high speed links, design methodologies description | |
Sabrina received her B.A.Sc in Engineering Science (EE option) from the University of Toronto in 2008 and is currently an MS/PhD student working under the supervision of Professor Horowitz. Prior to coming to Stanford, she has had research experience in areas of multimedia communication, quantum mechanics and DCO design. In addition, she has worked at Gennum on ASIC verification and testing. Her research interests include analog/mixed-signal circuit design, optoelectronics and CMOS integration, high speed links and design methodologies. She is currently working on an ADC project.
Byong Chan Lim
I received B.S. and M.S. degrees in electronic engineering from Hanyang University, Seoul, Korea, in 1997 and 2002, respectively. I am currently working toward the Ph. D. degree in electrical engineering at Stanford University. From 2003 to 2007, I had been working on analog IP developement for LG electronics.
Farshid Moussavi
Farshid is doing research on algorithms for cryo electron tomography with Prof. Mark Horowitz and Prof. Daphne Koller in Electrical Engineering at Stanford. His research interests include computer vision, probabilistic inference, machine learning, optimization, applications to biological imaging problems, as well as signal processing hardware/system architecture. He is a PhD candidate in Stanford EE department, and holds an MSEE from University of California at Berkeley as well as a BSEE (Summa Cum Laude) from University of Idaho. He has spent some time in industry prior to coming to Stanford in 2005 to pursue his PhD. He has been involved in the design of numerous networking and signal processing ASICs at Cisco Systems, Aptina Imaging, HP, and some startups. More recently he has consulted for Apple Computer. He is the author of 7 patents (2 granted and 5 pending).
Ofer Shacham
| Gates 320 | (650) 725-3657 |
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | http://stanford.edu/~shacham/ |
| Research Interests: Computer Architecture, VLSI design | |
Ofer is a PhD student at Stanford University’s EE department. His fields of research, under the advisory of Prof. Mark Horowitz, include Parallel Computer Architectures, ASIC design and verification, and High Performance Computing. He holds a Masters in Electrical Engineering from Stanford University and a Bachelors in Electrical Engineering and Computer Science from Tel-Aviv University. Prior to coming to Stanford, Ofer was working at IBM Labs in Israel, on ASIC design and verification, for high performance computing. Ofer's experience also includes 5 years of active service in an elite Israeli Navy unit.
Pete Stevenson
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | |
| Research Interests: design tools for digital circuits | |
Pete is a Ph.D. student at Stanford University working in the field of circuit design, under the direction of professor Mark Horowitz. He aspires to develop innovative design tools for digital circuits. He is interested in closing the gap between a design implemented by HDL synthesis and a design optimized by exhaustive customization. Hailing from Tulsa, OK, Pete attended the U.S. Naval Academy from 1996 to 2000. After being commissioned as an officer in the U.S. Navy, he attended Stanford to obtain an MSEE (2002). Following this, he served on board a nuclear powered submarine, the USS Los Angeles (SSN-688) stationed in Pearl Harbor, Hawaii. Subsequent to the tour at sea, Pete taught a basic network analysis class and an introduction to communications systems class at the U.S. Naval Academy, from 2006 to 2008. Pete is married and lives with his wife, Siejen, in Menlo Park, CA. His hobbies include surfing, golf, and reading.
Eino-Ville Talvala
| Gates 376 | |
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | http://graphics/~talvala/ |
| Research Interests: Computational Photography, Projectors, Computer Architecture | |
Eino-Ville works with Prof. Horowitz and Prof. Marc Levoy on computational photography, specifically focusing on removing glare from high-dynamic-range photographs. He is also helping out with the Camera 2.0 project, and in the past has worked with projector and camera arrays, 3D displays, and measuring light transport in a scene. He received his undergraduate degree from the California Institute of Technology, where he was involved in asynchronous VLSI research.
Megan Wachs
| Gates 320 | |
| This e-mail address is being protected from spambots. You need JavaScript enabled to view it | http://www.stanford.edu/~wachs |
| Research Interests: VLSI design and verification, and parallel architectures | |
Megan Wachs has been a MS/PhD student at Stanford since 2005. Her research interests include VLSI design and verification, and parallel architectures. In 2006 she started helping with the verification of the Stanford Smart Memories CMP, and is now working on the Chip Generator Project. She has worked as an intern at Cryptography Research, Inc, in San Francisco, as well as at Celestica, Shanghai. She received her BS from Brown University in 2005 in Electrical Engineering.
Gordon Wan
Gordon received his BS in Electrical Engineering and Mathematics from the University of Texas at Austin in 2005, and his
MS in Electrical Engineering from Stanford University in 2007. He is currently a PhD candidate under Prof. Mark Horowitz at Stanford University. He has received the James F. and Mary Lynn Gibbons Fellowship, the Stanford Graduate Fellowship, and the Pan Wen Yuan Scholarship. He ranked 2nd in Stanford PhD Qualifying Exam. His research interest is in CMOS image sensor, digital imaging, and solid-state devices.
Alumni
| Name | Thesis | |
|---|---|---|
| Valentin Abramzon | Analog-to-digital converters for high-speed links | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Elad Alon | Measurement and Regulation of On-Chip Power Supply Noise | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Amir Amirkhany | This e-mail address is being protected from spambots. You need JavaScript enabled to view it | |
| Bharadwaj Amrutur | Design and Analysis of Fast Low Power SRAMs | |
| Jules Bergmann | ||
| Tom Chanak | Netlist Processing for Custom VLSI via Pattern Matching | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Kun-Yung Chang | Design of a CMOS Asymmetric Serial Link | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Mark Dean | STRIP: A Self-Timed RISC Processor | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Bill Ellersick | Data Converters for High Speed CMOS Links | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Azita Emami-Neyestanak | Design of CMOS Receivers for Parallel Optical Interconnects | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Amin Firoozshahian | Smart Memoires: A Reconfigurable Memory System Architecture | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Jim Gasbarro | Architecture for High-Performance Single-Chip VLSI Testers | Rambus |
| Ricardo Gonzalez | Low-Power Processor Design | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| David Harris | Skew-Tolerant Circuit Design | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Ron Ho | On-Chip Wires: Scaling and Efficiency | Sun Labs |
| Richard Ho | Validation Tools for Complex Digital Designs | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Mike Johnson | Super-Scalar Processor Design | AMD |
| Russell Kao | Piecewise Linear Models for Switch-Level Simulation | Sun Labs |
| Hema Kapadia | Partitioning-Driven Convergence in the Design of Random-Logic Blocks | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Jaeha Kim | Design of CMOS Adaptive-Supply Serial Links | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Francois Labonte | A Stream Virtual Machine | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Hae-Chang Lee | An estimation approach to clock and data recovery | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| David Lie | Architectural Support for Copy and Tamper-Resistant Software | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Dean Liu | A Framework for Designing Reusable Analog Circuits | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Ken Mai | Design and Analysis of Reconfigurable Memories | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| John Maneatis | Precise Delay Generation Using Coupled Oscillators | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Bita Nezamfar | Energy-performance tunable circuits | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Samuel Palermo | Design of High-Speed Optical Interconnect Transceivers | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Arturo Salz | Incremental Tools for the Design and Verification of VLSI Circuits | |
| Mark Santoro | Design and Clocking of VLSI Multipliers | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Stefanos Sidiropoulos | High Performance Inter-Chip Signalling | Aeluros |
| Rich Simoni | Cache Coherence Directories for Scalable Multiprocessors | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Mike Smith | Support for Speculative Execution in High-Performance Processors | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Alex Solomatnikov | Polymorphic Chip Multiprocessor Architecture | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Jeff Solomon | The ChipMap: Visualizing Large VLSI Physical Design Datasets | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Don Stark | Analysis of Power Supply Networks in VLSI Circuits | Aeluros |
| Vladimir Stojanovic | Channel Limited High-Speed Links: Modeling, Analysis and Design | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Jim Weaver | Measuring supply currents in printed boards | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Gu-Yeon Wei | Energy-Efficient I/O Interface Design with Adaptive Power-Supply Regulation | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Dan Weinlader | Precision CMOS Receivers for VLSI Testing Applications | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Bennet Wilburn | High Performance Imaging Using Arrays of Inexpensive Cameras | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Ted Williams | Self-Timed Rings and their Application to Division | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Drew Wingard | High-Speed BiCMOS Memories | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Vicky Wong | Characterizing the Parallel Performance and Soft Error Resilience of Probabilistic Inference Algorithms | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Chih-Kong Ken Yang | Design of High-Speed Serial Links in CMOS | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |
| Evelina Yeung | High-performance & low-cost parallel links | This e-mail address is being protected from spambots. You need JavaScript enabled to view it |



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