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# Title Authors Year Type of Publication
 
Results 76 - 100 of 188
0 Adaptive Supply Serial Links With Sub-1-V Operation and Per-Pin Clock Recovery J. Kim, M. Horowitz 2002 article
1 A Tracking PLL with an FIR Loop Filter D. Liu, H. Johansson, J. Kim, M. Horowitz 2002 article
2 Do-It-Yourself Computers K. Mai 2001 misc
3 An Efficient Digital Sliding Controller for Adaptive Power Supply Regulation Jaeha Kim 2001 misc
4 An Efficient Digital Sliding Controller for Adaptive Power Supply Regulation J. Kim, M. Horowitz 2001 article
5 The Future of Wires R. Ho, K. Mai, M. Horowitz 2001 article
6 A Serial Link Based on 8 GSa/s A/D and D/A Converters in 0.25um CMOS W. Ellersick, C.-H. Yang, V. Stojanovic, S. Modjtahedi, M. Horowitz 2001 article
7 A Scalable Bit-rate High-Speed I/O Interface with Adaptive Power-Supply Regulation Jaeha Kim 2001 misc
8 A Serial Link Based on 8 GSa/s A/D and D/A Converters in 0.25um CMOS C.-H. Yang, V. Stojanovic, S. Modjtahedi, M. Horowitz, W. Ellersick 2001 article
9 Fast low-power decoders for RAMs B. Amrutur 2001 article
10 An introduction to gnuplot Ron Ho 2001 misc
11 Fast SPICE Simulators: A Survey Jaeha Kim 2001 misc
12 Using Texture Mapping with Mipmapping to Render a VLSI Layout Jeff Solomon, Mark Horowitz 2001 article
13 Noise and noise analysis tools Ron Ho 2001 misc
14 A Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation G. Wei, J. Kim, D. Liu, S. Sidiropoulos, M. Horowitz 2000 misc
15 A Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation G. Wei, J. Kim, D. Liu, S. Sidiropoulos, M. Horowitz 2000 article
16 A Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation G. Wei, J. Kim, D. Liu, S. Sidiropoulos, M. Horowitz 2000 article
17 Speed and Power Scaling of SRAM's B. Amrutur, M. Horowitz 2000 article
18 A 0.3-um CMOS 8-Gb/s 4-PAM serial link transceiver R. Farjad-Rad, C.-K.K. Yang, M. Horowitz 2000 article
19 A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per pin skew compensation E. Yeung, M. Horowitz 2000 article
20 An Eight Channel 36GSample/s CMOS Timing Analyzer D. Weinlader, R. Ho, C.-K. Yang, M. Horowitz 2000 misc
21 An Eight Channel 36GSample/s CMOS Timing Analyzer D. Weinlader, R. Ho, C.-K. Yang, M. Horowitz 2000 article
22 Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers S. Sidiropoulos, D. Liu, J. Kim, G. Wei, M. Horowitz 2000 article
23 Design of High-Performance & Low-Cost Parallel Links Evelina Yeung 2000 phdthesis
24 A 2.4Gbps/pin Simultaneous Bidirectional Parallel Link with Per Pin Skew Compensation E. Yeung & M. Horowitz 2000 misc