| 0 |
Life After Silicon: An Oxymoron? |
M. Horowitz |
2000 |
misc |
|
| 1 |
Layout design rules/trends |
Ron Ho |
2000 |
misc |
|
| 2 |
Smart Memories: A Modular Reconfigurable Architecture |
K. Mai, T. Paaske, N. Jayasena, R. Ho, W. Dally, Mark Horowitz |
2000 |
article |
|
| 3 |
Smart Memories: A Modular Reconfigurable Architecture |
K. Mai, T. Paaske, N. Jayasena, R. Ho, W. Dally, M. Horowitz |
2000 |
misc |
|
| 4 |
Architectural Support for Copy and Tamper Resistant Software |
D. Lie, C. Thekkath, M. Mitchell, P. Lincoln, D. Boneh, J. Mitchell, M. Horowitz |
2000 |
article |
|
| 5 |
VLSI Scaling for Architects |
M. Horowitz |
2000 |
misc |
|
| 6 |
Visualizing Physical CAD |
J. Solomon |
2000 |
misc |
|
| 7 |
A Fully Digital, Energy-Efficient, Adaptive Power-Supply Regulator |
G. Wei, M. Horowitz |
1999 |
article |
|
| 8 |
Wires: A User's Guide |
M. Horowitz, R. Ho, K. Mai |
1999 |
misc |
|
| 9 |
Scaling implications for CAD |
R. Ho, K. Mai, M. Horowitz |
1999 |
article |
|
| 10 |
The Future of Wires |
M. Horowitz, R. Ho, K. Mai |
1999 |
article |
|
| 11 |
GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link |
W. Ellersick, C.-K. K. Yang, M. Horowitz, W. Dally |
1999 |
article |
|
| 12 |
A 0.3-um CMOS 8-Gb/s 4-PAM serial link transceiver |
R. Farjad-Rad, C.-K. K. Yang, M. Horowitz, T. Lee |
1999 |
article |
|
| 13 |
A 32x32 CMOS crossbar chip using asymmetric serial links |
K.-Y. K. Chang, S. Chuang, N. McKeown, M. Horowitz |
1999 |
article |
|
| 14 |
A 0.4-um CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter |
R. Farjad-Rad, C.-K. K. Yang, M. Horowitz, T. Lee |
1999 |
article |
|
| 15 |
Scaling implications for CAD |
R. Ho, K. Mai, M. Horowitz |
1999 |
misc |
|
| 16 |
Improving Coverage Analysis and Test Generation for Large Designs |
J. Bergmann, M. Horowitz |
1999 |
article |
|
| 17 |
Timing analysis including clock skew |
D. Harris, D. Liu, M. Horowitz |
1999 |
article |
|
| 18 |
Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology |
H. Kapadia, M. Horowitz |
1999 |
article |
|
| 19 |
Vex - A CAD toolbox |
J. Bergmann, M. Horowitz |
1999 |
article |
|
| 20 |
Low-Power SRAM Design Using Half-Swing Pulse-Mode Techniques |
K. Mai, T. Mori, B. Amrutur, R. Ho, B. Wilburn, M. Horowitz |
1998 |
article |
|
| 21 |
A replica technique for wordline and sense control in low-power SRAMs |
B. Amrutur, M. Horowitz |
1998 |
article |
|
| 22 |
A 1V 0.9mW at 100MHz 2k*16b SRAM utilizing a half-swing pulsed decoder and write-bus architecture in 0.25um dual-Vt CMOS |
T. Mori, B. Amrutur, K. Mai, M. Horowitz, I. Fukushi, T. Izawa, S. Mitarai |
1998 |
article |
|
| 23 |
A 0.5um CMOS 4Gb/s serial link transceiver with data recovery using oversampling |
C.-K. K. Yang, R. Farjad-Rad, M. Horowitz |
1998 |
article |
|
| 24 |
A 2 Gb/s/pin CMOS asymmetric serial link |
K. K.-Y. Chang, W. Ellersick, T.-S. Chuang, S. Sidiropoulos, M. Horowitz |
1998 |
article |
|
Papers
