1 Pre-Tape-out Checks

Pre-Tape-out Checks

Before you send out a chip for fabrication be sure to run all of the tests listed below. Most of these tests originated by someone realizing a little too late there was a problem with their layout.

  1. Clean-up DRC violations.
    In Magic do the following, :drc check :drc catchup :drc count :write force :ext :cif or calma
  2. Check labels.
    Labels which differ only in the capitalization of letters are merged by IRSIM. Thus they appear to be shorted even if there is no physical connection between them. This script converts all labels to lowercase and then uses gemini to compare the designs. This test also checks that all Vdd and Gnd nodes, which are magically merged in IRSIM, are actually connected.
  3. Generate CIF
    Even if your design is DRC clean there can still be violations when generating CIF output. Write out the design as CIF (make sure there are no warnings) and then read it back in. There should still be no DRC violations. Then extract this new layout, remove all labels and compare with previous network. This ensures the cifout process will generate what you think it will.
  4. Routing through well.
    Signals can accidentally be routed through the wells. Extract your design using scmosWR tech file, which leaves wells unconnected. Compare the extracted sim file to the original design using gemini.
  5. Uncontacted wells.
    There are two special extraction styles (check_nwell, check_pwell) that you can use to check that all the wells are contacted. If there are any capacitors in the file one or more of your wells are not correctly plugged.
  6. Shottky diode.
    Need to get info
  7. Antenna test.
    Metal can act as antena attracting ions during the fabrication process. Extract your design then use ext2ant (??).
  8. LVL - Layout Versus Layout Comparison
    Use gemini to compare the netlist from the gdsii (or cif) and the netlist from the layout (pre-gdsii or pre-cif).

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