IRSIM Verilog Interface

Bug Warning!

Ken Yang just reported a bug in RsimVerilog (3/20/97). This bug should only be present in the old Ultrix executable on chroma. Using a bit-select of a register in $rsim_log_input or any other function will cause a core dump. The work-around is to use only wire signals as arguments to the functions or use a different version of the simulator.

Using Verilog to generate IRSIM vectors

You can use Verilog to generate a .cmd file (batch command file) for IRSIM. By using a special snooper module you can run the same simulations on the extracted Magic layout. The batch command file includes assertion for all the outputs. Differences in the Verilog output from the IRSIM output are automatically flagged.

You can use Verilog to generate IRSIM vectors if:

You can make your Verilog do what you want your circuit to do.
The nets you want to stimulate and verify exist in your Verilog module.
Some node in your Verilog specifies the direction of each bidirectional node to stimulate/verify.

Things will be easier if:

Your outputs and bidirectional ports have "v" or "s" timing types.
The Verilog names for those ports end with underbar-timingtime-phase (like foo_v2).
IRSIM names for buses end in bracketed numbers just as thier Verilog counterparts (bus_s1[0], bus_s1[1], bus_s1[2], etc.)

The steps are:

Create a "snooper" module
Instantiate the snooper in your Verilog
Run the Verilog as usual (remember to use the -x flag)
Quit Verilog
Fire up IRSIM
Run "versim.cmd", which your Verilog run generated
Look for messages from IRSIM, "Assert Failed" - no news is good news

There is a nifty perl script that will do 3-7 for you. Look for it in the Hacks page.

Creating a Snooper Module

A snooper module has all of the relavent nodes of your Verilog model as inputs. It works by calling PLI functions like "$rsim_log_input" and "$rsim_log_output" whenever the appropriate signals change or need to be checked in Verilog. The PLI functions create the file "versim.cmd".

There's a program called snoopgen in the class directory. It will automatically generate the snooper.v module for you. All it needs is an input file that lists the nodes you want to snoop and whether they are inputs, outputs, or input/outputs.

Here is an example of its input file:

i Phi1 i Phi2 phi2 c Phi1 c Phi2 i input i inbus[3:0] inbus o outbus_s1[7:0] o output_v2 b control_node i bibus_v1[3:0] irsimbibus b control_node o biput_s2

Each line specifies either a clock, an input, an output, or a bidirectional port. Clock names and timing-type suffixes are used to match phases. "i", "o", and "b" lines include an optional IRSIM name, which can be different from the Verilog name.

Clocks will usually also be inputs.

For vectors, only put the range on the Verilog name.

The "i" or "o" in a "b" line specifies the sense of the control node. If "i" is specified, the biput is an input when the control node is high.

If clocks or biput-controlling nodes are also inputs or outputs, list the inputs or outputs earlier than the "c" and "b" lines in the input file.

You will probably be able to take a snooper module directly from snoopgen. If not, running snoopgen will still illustrate the form of snooper modules.

A typical use of snoopgen from the UNIX command like would look like:

snoopgen system.in > snooper.v

Note that snoopgen does not automatically make an output file. You have to explicity dump the output to a file. The file "system.in" would be a snoopgen input file.

If you know what you are doing you can generate your Snooper file by hand. Just look at what the output of snoopgen looks like and you should be able to figure out what is going on.

Instantiating the Snooper in your Verilog

It can go wherever you want, but it may have to be within the module you're checking or the next one above to have easy access to the nodes it needs. You may have to access some nodes through the hierarchy - e.g., padframe.pad11.ENABLE

Running the Verilog

Run Verilog with the -x option. This causes all buses to be expanded into single bit signals.

You may want to run the Verilog for a fixed period of time, by firing it up in interactive mode (-s on the command line) and running something like:

C1> #1000 $stop; C2> .

Running IRSIM

Running Irsim will be as simple as typing "versim", but you may first want to set up analyzers, checking power and ground for fragments, etc.

It should not be necessary to use the irsim "clock" command.

Advanced Features

For some applications you need to check IRSIM signal value when an IRSIM event happens not when a Verilog event happens. For these applications the original assert IRSIM command is not powerful enough. Look at the assertwhen command in the IRSIM man page. You will have to modify your Snooper module appropriately.

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