CAD Tools

Reorganization of CAD Tool flow

Minutes from meeting of 5/8/03


The former FTP site is here...

We previously provided IRSIM and Magic from anonymous ftp. Now they are available here.

Magic is now maintained by Cornel here


Design Flow

We use an eclectic mix of public and comercial tools to design chips. Our design flow is roughly as follows,

  1. Develop a behavioral model in Verilog.
    We use simulators from Cadence and Synopsys. The waveform viewer of our choice is Magellan originally from System Science, now owned by Cadence renamed SimWave.
  2. Develop circuit schematics using Sue.
    Sue is a cool schematic editor written completely in Tcl/Tk. It was developed by Lee Tavrow. Every circuit element is a Tcl procedure. We can give you some tips to use Sue effectively.
  3. Verify circuit implementations using
    We use either Avant! AvanWaves or nst (the companion to Sue) to view the output of Star-HSPICE.
  4. Circuit layout using Magic.
    Although there seems to be some disagreement among some of our group members, most people prefer Magic because it is simple to use yet so powerful. We have made some effort to move to commercial tools but have never been succesful.
  5. Layout validation using IRSIM.
    We have developed code (we call it RsimVerilog) which uses the Verilog model to drive the IRSIM inputs. If your design is too big or has some circuits which give IRSIM indigestion you can use cy, written by Tom Chanak, to remove some transistors.
  6. Layout validation using Nassda's HSIM.
    Some circuits cannot be easily simulated with IRSIM. Instead we use HSIM, a fast circuit simulator, to validate these designs.
  7. Schematic comparison.
    We use Gemini to ensure that the layout matches the schematics. Gemini is a good tool but can be a little bit hard to use so here are some tips for you.
  8. Pre-tape-out checks.
    Very important step. Don't send something off before doing this. These are a collection of scripts that we have developed over the years to eliminate simple mistakes in the layout. There were some previous student who wished they had these scripts before they tapedout. Of course, they didn't write the script until they found out their chip was not working.

    

Tips, Tricks, and Hacks

Sue Gemini Magic
RsimVerilog
Hacks